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general description the max1338 14-bit, analog-to-digital converter (adc)offers four simultaneously sampled, fully differential input channels, with independent track-and-hold (t/h) circuitry for each channel. the input channels are individually software programmable for input ranges of ?0v, ?v, ?.5v, and ?.25v. the input channels feature fault tol- erance to ?7v. the internal t/h circuits have a 16ns aperture delay and 100ps aperture-delay matching. a 14-bit parallel bus provides the conversion result with a maximum per-channel output rate of 150ksps (600ksps for all four channels). the max1338 has an on-board oscillator and 2.5v internal reference. an external clock and/or reference can also be used. the max1338 operates from a +5v supply for analog inputs and digital core. the device operates from a +2.7v to +5.25v supply for the digital i/o lines. the max1338 features two power-saving modes: standby mode and shutdown mode. standby mode allows rapid wake-up and reduces quiescent current to 4ma (typ), and shut- down mode reduces sleep current to less than 10? (typ). the max1338 is available in an 8mm x 8mm x 0.8mm, 56-pin, thin qfn package. the device operates over the extended -40? to +85? temperature range. applications multiple-channel data recordersvibration analysis motor control: 3-phase voltage, current, and power measurement optical communication equipment features ? 150ksps sample rate per channel ? all four input channels simultaneously sampled 16ns aperture delay100ps aperture-delay matching ? channel-independent software-selectable inputrange: ?0v, ?v, ?.5v, ?.25v ? ?7v fault-tolerant inputs ? dynamic performance at 10khz input snr: 77dbsinad: 76db sfdr: 98dbc thd: -83dbc ? dc performance inl: ? lsbdnl: ? lsb offset error: ? lsb gain error: ?.1% fsr ? 14-bit parallel interface ? internal clock and reference voltage ? +5v analog and digital supplies ? +2.7v to +5.25v digital i/o supply ? 56-pin thin qfn package (8mm x 8mm x 0.8mm) max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ________________________________________________________________ maxim integrated products 1 ordering information 19-3151; rev 1; 7/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max1338etn -40 c to +85 c 56 thin qfn-ep* * ep = exposed pad. pin configuration appears at end of data sheet. downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v drv dd to drgnd ....................................................-0.3v to +6v av dd to dv dd .......................................................-0.3v to +0.3v dgnd to drgnd ..................................................-0.3v to +0.3v agnd to dgnd.....................................................-0.3v to +0.3v agnd to drgnd ..................................................-0.3v to +0.3v ain0+, ain0-, ain1+, ain1-, ain2+, ain2-, ain3+, ain3- to agnd .....................................................-17v to +17v d0?13 to drgnd................................-0.3v to (drv dd + 0.3v) refadc, refp1, refp2, refn1, refn2, com1, com2 to agnd....................................................-0.3v to (av dd + 0.3v) intclk/ extclk to agnd.......................-0.3v to (av dd + 0.3v) cs , rd , wr , convst, to drgnd........-0.3v to (drv dd + 0.3v) shdn, standby, clk, eoc , eolc to drgnd ................................-0.3v to (drv dd + 0.3v) maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 56-pin thin qfn (derate 31.3mw /c above +70?) .... 2500mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? maximum junction temperature .....................................+150? lead temperature (soldering, 10s) .................................+300? junction to ambient thermal resistance ja ..................32?/w junction to case thermal resistance jc .........................2?/w electrical characteristics(av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd, 0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1. typical values are at t a = +25?. t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units static performance resolution n 14 bits integral nonlinearity inl (note 1) 1 3 lsb differential nonlinearity dnl no missing codes (note 1) 0.25 1 lsb offset error (note 1) 4 16 lsb offset-error temperaturecoefficient 5 ppm/? offset-error matching 10 lsb gain error offset nulled (notes 1, 2) 0.1 0.35 %fsr channel gain-error matching offset nulled 20 lsb gain-error temperaturecoefficient offset nulled 10 ppm/ c dynamic performance (at f in = 10khz, a in = -0.2dbfs) sampling rate per channel simultaneous on all channels 150 ksps signal-to-noise ratio snr (note 1) 75 77 db signal-to-noise plus distortion sinad (note 1) 74 76 db total harmonic distortion thd (note 1) -83 -80 dbc spurious-free dynamic range sfdr range 0 (note 1) 85 dbc channel-to-channel isolation (note 1) 80 db analog inputs (ain_) range set bits = (0,0) -10 +10 range set bits = (0,1) -5 +5 range set bits = (1,0) -2.5 +2.5 input differential voltage range range set bits = (1,1) -1.25 +1.25 v downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc _______________________________________________________________________________________ 3 electrical characteristics (continued)(av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd, 0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1. typical values are at t a = +25?. t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units range set bits = (0,0) -5 +5 range set bits = (0,1) -2.5 +2.5 range set bits = (1,0) -1.25 +1.25 input common-mode range range set bits = (1,1) -0.625 +0.625 v input resistance all settings 6.25 k ? input capacitance 15 pf small-signal bandwidth ssbw (note 1) 1 mhz full-power bandwidth fpbw (note 1) 75 khz internal reference (refadc) output voltage 2.475 2.5 2.525 v differential reference voltage refp refn 2.5 v output-voltage temperaturecoefficient 50 ppm/ c load regulation 5 v/ma external reference refadc voltage input range 2.0 2.5 3.0 v refadc input current (note 3) -250 +250 ? refadc input resistance r ref 5k ? refadc input capacitance 15 pf track/hold (t/h) aperture delay t ad (note 1) 16 ns aperture-delay matching 100 ps aperture jitter t aj (note 1) 50 ps rms clock-select input (intclk/ extclk ) input-voltage high v ih 0.7 x av dd v input-voltage low v il 0.3 x av dd v digital interface and control inputs ( cs , rd , wr , convst, shdn, clk, standby) input-voltage high v ih 0.7 x drv dd v input-voltage low v il 0.3 x drv dd v input hysteresis 50 mv input capacitance c in 15 pf downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 4 _______________________________________________________________________________________ electrical characteristics (continued)(av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd, 0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1. typical values are at t a = +25?. t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units input current i in v in = 0 or drv dd ? ? digital interface and control outputs ( eoc , eolc ) output-voltage high v oh sourcing 0.8ma drv dd - 0.6 v output-voltage low v ol sinking 1.6ma 0.4 v parallel digital i/o (d0?7) output-voltage high v oh sourcing 0.8ma drv dd - 0.6 v output-voltage low v ol sinking 1.6ma 0.4 v leakage current 1 a tristate output capacitance rd = 1 or cs = 1 15 pf input-voltage high v ih 0.7 x drv dd v input-voltage low v il 0.3 x drv dd v input hysteresis 50 mv input capacitance c in 15 pf input current i in v in = 0 or drv dd ? ? parallel digital outputs (d8?13) output-voltage high v oh sourcing 0.8ma drv dd - 0.6 v output-voltage low v ol sinking 1.6ma 0.4 v leakage current 1 a tristate output capacitance 15 pf power supplies analog supply voltage av dd 4.75 5 5.25 v digital supply voltage dv dd 4.75 5 5.25 v parallel digital i/o supply voltage drv dd 2.70 5.25 v 41 60 shdn = 1 0.005 0.1 analog supply current ai dd standby = 1, shdn = 0 4.2 5 ma 3 shdn = 1 0.001 0.05 digital supply current di dd standby = 1, shdn = 0 0.001 0.05 ma 3 shdn = 1 0 0.05 digital driver supply current dri dd standby = 1, shdn = 0 0 0.05 ma analog power-supply rejection 4.75v to 5.25v (note 1) 75 db downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc _______________________________________________________________________________________ 5 electrical characteristics (continued)(av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0f and 0.1? from com1 to agnd, 0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1. typical values are at t a = +25?. t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units timing characteristics (figures 4, 5, and 6) internal clock 2.9 3.2 3.5 ? time to first conversion result t eoc1 external clock 16 clk cycles internal clock 600 ns time to subsequent conversions t next external clock 3 clk cycles internal clock 0.2 convst pulse-width low t convst external clock 0.1 ? cs pulse width t cs 30 ns rd pulse-width low t rdl 30 ns rd pulse-width high t rdh 30 ns wr pulse-width low t wrl 30 ns cs to wr setup time t ctw 0n s wr to cs hold time t wtc 0n s cs to rd setup time t ctr 0n s rd to cs hold time t rtc 0n s data access time( rd low to valid data) t acc figure 1 30 ns bus relinquish time( rd high to d_ high-z) t req figure 1 5 30 ns clk rise to end-of-conversion( eoc ) rise/fall delay t eocd 20 ns clk rise to end-of-last-conversion ( eolc ) fall delay t eolcd 20 ns convst rise to eolc fall delay t cveolcd 20 ns internal clock 180 200 ns eoc pulse-width low t eoc external clock 1 clk cycle wake-up time from standby 7 s wake-up time from shutdown all bypass capacitors discharged 5 ns downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 6 _______________________________________________________________________________________ electrical characteristics (continued)(av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0f and 0.1? from com1 to agnd, 0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1. typical values are at t a = +25?. t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units eoc fall to rd fall setup time t eocrd 0n s eolc fall to rd fall setup time t eolcrd 0n s input data setup time t dtw 10 ns input data hold time t wtd 10 ns external clk period t clk 166 200 ns external clk high period t clkh logic sensitive to rising edges 60 ns external clk low period t clkl logic sensitive to rising edges 60 ns external clock frequency f clk (note 4) 1 6 mhz internal clock frequency f int 5.0 5.25 5.5 mhz convst high to clk edge t cntc 30 ns quiet time t quiet 600 ns note 1: see definition for this parameter in the definitions section. note 2: differential reference voltage (refp?efn) error nulled. note 3: this is the load the max1338 presents to an external reference at refadc. note 4: minimum clk frequency is limited only by the internal t/h droop rate. limit the time between the rising edge of convst tothe falling edge of eolc to a maximum of 0.25ms. 1.6v 1.6ma 0.8ma 50pf to output pin figure 1. load circuit for data access time and bus-relinquish time downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc _______________________________________________________________________________________ 7 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -8192 -4096 0 4096 8192 integral nonlinearity vs. output code max1338 toc01 output code (decimal) inl (lsb) -0.6 -0.2-0.4 0.2 0 0.4 0.6 -8192 0 -4096 4096 8192 differential nonlinearity vs. output code max1338 toc02 output code (decimal) dnl (lsb) -6 -4-5 -2-3 -1 0 4.75 4.95 4.85 5.05 5.15 5.25 offset error vs. supply voltage max1338 toc03 av dd (v) offset error (lsb) channel 0 channel 2 channel 1 channel 3 -15 -5 -10 50 10 15 -40 10 -15 35 60 85 offset error vs. temperature max1338 toc04 temperature ( c) offset (lsb) gain error vs. supply voltage max1338 toc05 supply voltage (v) gain error (%fs) 5.15 5.05 4.85 4.95 -0.20 -0.19 -0.18 -0.17 -0.16 -0.15 -0.14 -0.13-0.21 4.75 5.25 ch1 ch2 ch3 ch0 reference error nulled -0.15 -0.05-0.10 0.05 0 0.10 0.15 -40 10 -15 35 60 85 gain error vs. temperature max1338 toc06 temperature ( c) gain error (%fs) 0 20001000 40003000 5000 6000 -2 0 -1 1 2 output histogram (dc input) max1338 toc07 digital output code counts 61 1646.25 4584.25 1802.75 97.25 offset normalized -0.8 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 05 01 0 0 150 200 analog input bandwidth max1338 toc08 f in (khz) attenuation (db) -0.7 t ypical operating characteristics (av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd,0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1.) downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 8 _______________________________________________________________________________________ -125 -100 -50-75 -25 0 03 0 15 45 60 75 fft at f sample = 150ksps, f in = 10khz max1338 toc10 frequency (khz) amplitude (db) 70 7271 7473 7675 77 7978 80 1 345 2 678910 signal-to-noise ratio vs. clock frequency max1338 toc11 f clk (mhz) snr (db) 70 7271 7473 7675 77 7978 80 1 345 2 678910 signal-to-noise plus distortion vs. clock frequency max1338 toc12 f clk (mhz) snr (db) -110 -106-108 -102-104 -98 -100 -96 -92-94 -90 1 345 2 678910 total harmonic distortion vs. clock frequency max1338 toc13 f clk (mhz) thd (db) 80 85 90 95 100 105 110 13 24 5678910 spurious-free dynamic range vs. clock frequency max1338 toc14 f clk (mhz) sfdr (db) 70 7372 71 74 75 76 77 78 79 80 2.0 2.4 2.2 2.6 2.8 3.0 signal-to-noise ratio vs. reference voltage max1338 toc15 v refadc (v) snr (db) 70 7372 71 74 75 76 77 78 79 80 2.0 2.4 2.2 2.6 2.8 3.0 signal-to-noise plus distortion vs. reference voltage max1338 toc16 v refadc (v) sinad (db) -105 -99 -101-103 -97 -95 -93 -91 -89 -87 -85 2.0 2.4 2.2 2.6 2.8 3.0 total harmonic distortion vs. reference voltage max1338 toc17 v refadc (v) thd (db) 80 9085 100 95 105 110 2.0 2.4 2.2 2.6 2.8 3.0 spurious-free dynamic range vs. reference voltage max1338 toc18 v refadc (v) sfdr (db) t ypical operating characteristics (continued) (av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd,0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1.) downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc _______________________________________________________________________________________ 9 42.4 42.6 42.8 43.0 43.2 43.4 43.6 43.8 44.0 4.75 4.85 4.95 5.05 5.15 5.25 supply current vs. supply voltage max1338 toc19 av dd (v) a| dd + d| dd (ma) excludes driver current 40 4241 4443 45 46 -40 10 -15 35 60 85 supply current vs. temperature max1338 toc20 temperature ( c) a| dd + d| dd (ma) excludes driver current 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.75 3.25 3.75 4.25 4.75 5.25 driver supply current vs. supply voltage max1338 toc21 drv dd (v) dr| dd (ma) 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 -40 -15 10 35 60 85 driver supply current vs. temperature max1338 toc22 temperature ( c) dr| dd (ma) drv dd = 3v 2.4978 2.49802.4979 2.49832.4982 2.4981 2.49862.4985 2.4984 2.4987 4.75 4.95 4.85 5.05 5.15 5.25 reference voltage vs. supply voltage max1338 toc23 av dd (v) v refadc (v) 2.490 2.4942.492 2.4982.496 2.5022.500 2.504 -40 10 -15 35 60 85 reference voltage vs. temperature max1338 toc24 temperature ( c) v refadc (v) 40 5045 6055 65 70 4.75 4.95 4.85 5.05 5.15 5.25 shutdown current vs. supply voltage max1338 toc25 av dd (v) a| dd ( a) shdn = av dd t ypical operating characteristics (continued) (av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd,0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1.) downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 10 ______________________________________________________________________________________ 4.00 4.104.05 4.204.15 4.25 4.30 -40 10 -15 35 60 85 standby current vs. temperature max1338 toc28 temperature ( c) a| dd (ma) standby = av dd 4.8 5.0 5.45.2 5.6 5.8 4.75 4.95 4.85 5.05 5.15 5.25 conversion time vs. supply voltage max1338 toc29 av dd (v) conversion time ( s) internal clock 4.8 5.0 5.45.2 5.6 5.8 -40 10 -15 35 60 85 conversion time vs. temperature max1338 toc30 temperature ( c) conversion time ( s) internal clock -4 -3 -2 -1 0 1 2 3 4 -17.0 -8.5 0 8.5 17.0 analog input current vs. analog input voltage max1338 toc31 input voltage (v) input current (ma) t ypical operating characteristics (continued) (av dd = dv dd = +5.0v, drv dd = +3.0v, agnd = dgnd = drgnd = 0, intclk/ extclk = agnd, f clk = 5mhz, input range = ?0v, refp2 = refp1, refn2 = refn1, com1 = com2, 1.0nf from refadc to agnd, 1.0? and 0.1? from com1 to agnd,0.1? from refp1 to agnd, 0.1? from refn1 to agnd, 1.0? from refp1 to refn1.) 40 5045 6055 65 70 -40 10 -15 35 60 85 shutdown current vs. temperature max1338 toc26 temperature ( c) a| dd ( a) shdn = av dd 4.00 4.104.05 4.204.15 4.25 4.30 4.75 4.95 4.85 5.05 5.15 5.25 standby current vs. supply voltage max1338 toc27 av dd (v) a| dd (ma) standby = av dd downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 11 pin description pin name function 1, 7, 9, 17, 19 av dd analog power input. av dd is the power input for the analog section of the converter. connect a +4.75v to +5.25v power supply to av dd . bypass each av dd to agnd with a 0.1? capacitor very close to the device. bypass av dd to agnd with a bulk capacitor of at least 4.7? where power enters the board. connect all av dd pins to the same potential. 2 ain0+ channel 0 differential analog input 3 ain0- channel 0 differential analog input 4 ain1+ channel 1 differential analog input 5 ain1- channel 1 differential analog input 6, 8, 14, 16, 18, 20, 28 agnd analog ground. agnd is the power return for av dd . connect all agnds to the same potential. 10 ain2+ channel 2 differential analog input 11 ain2- channel 2 differential analog input 12 ain3+ channel 3 differential analog input 13 ain3- channel 3 differential analog input 15 intclk/extclk clock-select input. force intclk/ extclk high for internal clock mode. force intclk/ extclk low for external clock mode. 21 refadc adc reference bypass or input. refadc is the bypass point for an internally generated referencevoltage. bypass refadc with a 1.0nf capacitor to agnd. refadc can be driven externally by a precision external voltage reference. see the reference section and the typical operating circuit . 22 refp1 positive differential reference bypass point 1. connect refp1 to refp2. 23 refp2 positive differential reference bypass point 2. connect refp2 to refp1. bypass refp2 with a 0.1? capacitor to agnd. also bypass refp2 to refn2 with a 0.1? capacitor. 24 com1 common-mode voltage bypass point 1. connect com1 to com2. 25 com2 common-mode voltage bypass point 2. connect com2 to com1. connect a 1.0? capacitor fromcom2 to agnd. 26 refn1 negative differential reference bypass point 1. connect refn1 to refn2. 27 refn2 negative differential reference bypass point 2. connect refn2 to refn1. bypass refn2 with a0.1? capacitor to agnd. also bypass refn2 to refp2 with a 0.1? capacitor. 29 d0 data input/output bit 0 (lsb) 30 d1 data input/output bit 1 31 d2 data input/output bit 2 32 d3 data input/output bit 3 33 d4 data input/output bit 4 34 d5 data input/output bit 5 35 d6 data input/output bit 6 36 d7 data input/output bit 7 37 d8 data output bit 8 38 d9 data output bit 9 39 d10 data output bit 10 40 d11 data output bit 11 downloaded from: http:///
max1338 detailed description the max1338 simultaneously samples four differentialanalog inputs with internal t/h circuits, and sequentially converts them to a digital code with a 14-bit adc. output data is provided by a 14-bit parallel interface. at power-up, all channels default to a ?0v input range. program different input ranges (10v, ?v, ?.5v, or ?.25v) using the configuration register. different input ranges between ?2v and ?.0v are realized using an external reference. all channels offer input protection to?7v, independent of the selected input range. the internal clock operates the adc at 5mhz, or uses an external conversion clock from 1mhz to 6mhz. eoc goes low when the result of each conversion is avail- able, and eolc goes low when the last conversion result is available. standby and shutdown modes,selectable through logic-control inputs, save power between conversions. figure 2 shows a block diagram of the max1338. 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 12 ______________________________________________________________________________________ pin description (continued) pin name function 41 d12 data output bit 12 42 d13 data output bit 13 (msb) 43 drv dd digital i/o power-supply input. drv dd is the power input for the digital i/o buffers and drivers. connect a +2.7v to +5.25v power supply to drv dd . bypass drv dd to drgnd with a 0.1? capacitor very close to the device. 44 drgnd driver ground. drgnd is the power-supply return for drv dd . 45 eoc end-of-conversion output. eoc goes low to indicate the end of a conversion. eoc returns high after one clock period. 46 eolc end-of-last-conversion output. eolc goes low to indicate the end of the last conversion. eolc returns high when convst goes low for the next conversion sequence. 47 rd read input. forcing rd low initiates a read command of the parallel data bus, d0?13. d0?13 are high impedance while either rd or cs is high. 48 wr write input. forcing wr low initiates a write command for configuring the device through d0?7. 49 cs chip-select input. forcing cs low activates the digital interface. d0?13 are high impedance while either cs or rd is high. 50 convst convert start input. convst initiates the conversion process. the analog inputs are sampled on therising edge of convst. 51 clk external-clock input. clk accepts a 1mhz to 6mhz external clock signal. for externally clockedconversions, apply the clock signal to clk and force intclk/ extclk low. for internally clocked conversions, connect clk to dgnd and force intclk/ extclk high. 52 standby standby-control input. forcing standby high partially powers down the device but leaves all thereference-related circuitry alive. use standby instead of shdn when quick wake-up is required. 53 shdn shutdown-control input. force shdn high to place the device into full shutdown. when in fullshutdown, all circuitry within the device is powered down and all reference capacitors are allowed to discharge. allow 1ms for wake-up from full shutdown before starting a conversion. 54 dv dd d i g i tal p ow er - s up p l y inp ut. d v d d i s the p ow er i np ut for the d i g i tal ci r cui tr y. c onnect a + 4.75v to + 5.25v p ow er sup p l y to d v d d . byp ass d v d d to d gn d w i th a 0. 1f cap aci tor ver y cl ose to the d evi ce. 55, 56 dgnd digital ground. power return for dv dd . ? p exposed pad. connect to agnd. downloaded from: http:///
power-supply inputs three separate power supplies power the max1338. a+5v analog supply, av dd , powers the analog input and converter sections. a +5v digital supply, dv dd , powers the internal logic circuitry, and a +2.7v to +5v digitalsupply (drv dd ), powers the parallel i/o and the control i/o (see the typical operating circuit ). bypass the power supplies as indicated in the layout, grounding, and bypassing section. power-supply sequencing is not required for the max1338. analog inputs software-selectable input range the max1338 provides four independent, software-selectable, analog input voltage ranges for each chan- nel. the selectable input ranges are ? ref x 4 (the power-up default condition), ? ref x 2, ? ref , and ? ref x 0.5. using the 2.5v internal reference, the selectable input ranges are ?0v (power-up default),?v, ?.5v, and ?.25v. program the analog input ranges with the configuration register through the parallel i/o. see the configuration register section for programming details. input protection protection at the analog inputs provides ?7v fault immunity for the max1338. this protection circuit limits the current at the analog inputs to less than ?ma. input fault protection is active in standby, in shutdown, during normal operation, and over all input ranges. track and hold (t/h) to preserve relative phase information between inputchannels, each input channel has a dedicated t/h amplifier. the rising edge of convst represents the sampling instant for all channels. all samples are taken within an aperture delay (t ad ) of 16ns. the aperture delay of all channels is matched to within 100ps. max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 13 max1338 convst d13 dgnd av dd shdnclk interface and control 14-bit adc d0 dv dd agnd standby refadc s/h 4 x 14 sram output drivers 5k ? 2.500v intclk/extclk cs rd eoc eolc refn1 drgnd wr drv dd d8 d7 configuration register refn2 com1 com2 refp2 refp1 ain3+ ain3- s/h ain0- ain0+ 4 x 1 mux figure 2. functional diagram downloaded from: http:///
max1338 figure 3 shows the equivalent analog input t/h circuit for one analog input. as conversion begins, the t/h circuits hold the analog signals. after the 12th clock cycle (or 2.4? in internal clock mode) into the conversion process, the last ana- log input sample begins shifting through the converter, and the t/h circuits begin to track the analog inputs again in preparation for the next convst rising edge. due to the resistive load presented by the analog inputs, any significant analog input source resistance, r source , increases gain error. limit r source to a maximum of 20 ? to limit the effect to less than 0.1%. drive the input with a wideband buffer (>1mhz) that can drive the adc? input impedance. selecting an input buffer most applications require an input buffer to achieve 14-bit accuracy. although slew rate and bandwidth are important, the most critical specification is output imped- ance. use a low-noise, low-distortion amplifier with low output impedance, for best gain-accuracy performance. input bandwidth the input-tracking circuitry has a 1mhz small-signal bandwidth. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias fil- tering is recommended. data throughput the data throughput (f th ) of the max1338 is a function of the clock speed (f clk ). the max1338 operates from a 5mhz internal clock or an external clock between1mhz and 6mhz. for fastest throughput, read the con- version result during conversion (figure 5), and calcu- late data throughput using: where t quiet is the period of bus inactivity before the rising edge of convst. clock modes the max1338 provides an internal clock of 5mhz.alternatively, use an external clock of 1mhz to 6mhz. internal clock internal clock mode frees the microprocessor from theburden of running the adc conversion clock. for inter- nal-clock operation, connect intclk/ extclk to av dd and clk to drgnd. note that intclk/ extclk is ref- erenced to the analog power supply, av dd . total con- version time for all four channels using the internalclock is 6? (typ). f t f th quiet clk = + 1 26 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 14 ______________________________________________________________________________________ ain_ r1 max1338 r2 1.9v r1 || r2 = 6.25k ? c hold figure 3. simplified typical input circuit t cs t ctw t wrl t wtc t dtw d atain t wtd convst configuration register activates rd cs wr d0?7 figure 4. write timing downloaded from: http:///
external clock for external clock operation, force intclk/ extclk low and connect an external clock source to clk. use anexternal clock frequency from 1mhz to 6mhz with a duty cycle between 40% and 60%. choose a minimum clock frequency of 1mhz to prevent linearity errors caused by excessive droop in the t/h circuits. applications sections power-on reset at power-up, all channels default to a ?0v input range. after applying power, allow a 1ms wake-up time to elapse and perform one dummy conversion before initiating first conversion. power saving full shutdown during shutdown, the analog and digital circuits in themax1338 power down and the device draws less than 0.06ma from av dd , and less than 10? from dv dd . select shutdown mode using the shdn input. forceshdn high to enter shutdown mode. when coming out of shutdown, allow the 1ms wake-up and then perform one dummy conversion before making the first conversion. standby standby is similar to shutdown but the reference cir-cuits remain powered up, allowing faster wake-up. enter standby by forcing standby high. after coming out of standby, perform a dummy conversion before making the first conversion. digital interface the digital interface consists of two sections: a controli/o section and a parallel i/o section. the control i/o section includes the following control signals: chip select ( cs ), read ( rd ), write ( wr ), end of conversion ( eoc ), end of last conversion ( eolc ), convert start (convst), power-down (shdn), standby (standby),and external-clock input (clk). the bidirectional parallel i/o section sets the 8-bit input range configuration register using d0?7 (see the configuration register section) and outputs the 14-bit conversion result using d0?13. the i/o operations arecontrolled by the control i/o signals rd , wr , and cs . all parallel i/o bits are high impedance when either rd = 1 or cs = 1. figures 4, 5, and 6 and the timing character- istics section detail the operation of the digital interface. configuration register the max1338 uses an 8-bit configuration word to set theinput range for each channel. table 1 and table 2 describe the configuration word and the input-range settings. write to the configuration register by forcing cs and wr low, loading bits d0?7 onto the parallel bus, and thenforcing wr high. the configuration bits are latched on the rising edge of wr (figure 4). it is possible to write to the configuration register at any point during the conver-sion sequence. however, it will not be active until the next convert-start signal. at power-up, the configuration register contains all zeros, making all channels default to the maximum input range, -10v to +10v. shutdown and standby do not change the configuration register, but the configuration register can be programmed while the max1338 is in shutdown or standby modes. max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 15 i/o line register name function d0 ch0r0 channel 0 input range setting bit 0 d1 ch0r1 channel 0 input range setting bit 1 d2 ch1r0 channel 1 input range setting bit 0 d3 ch1r1 channel 1 input range setting bit 1 d4 ch2r0 channel 2 input range setting bit 0 d5 ch2r1 channel 2 input range setting bit 1 d6 ch3r0 channel 3 input range setting bit 0 d7 ch3r1 channel 3 input range setting bit 1 table 1. configuration register register setting ch_r0 ch_r1 selected input range allowable common-mode range 00 -10v to +10v ?v 01 -5v to +5v ?.5v 10 -2.5v to +2.5v ?.25v 11 -1.25v to +1.25v ?.625v table 2. input-range register settings downloaded from: http:///
max1338 starting a conversion internal clock for internal clock operation, force intclk/ extclk high. to start a conversion using internal clock mode,pull convst low for at least t convst . the t/h acquires the signal while convst is low. an eoc signal pulses low when the first result becomes available, and foreach subsequent result until the end of the conversion cycle. the eolc signal goes low when the last conver- sion result becomes available (figure 6). external clock for external clock operation, force intclk/ extclk low. to start a conversion using external clock mode,pull convst low for at least t convst . the t/h circuits track the input signal while convst is low. conversionbegins on the rising edge of convst. apply an exter- nal clock to clk. to avoid t/h droop degrading the sampled analog input signals, the first clk pulse must occur within 10? after the rising edge of convst and have a minimum 1mhz clock frequency. the first con- version result is available for read on the rising edge of the 17th clock cycle, and subsequent conversions on every 3rd clock cycle thereafter, as indicated by eoc and eolc . reading a conversion result reading during a conversion figure 5 shows the interface signals to initiate a read operation during a conversion cycle. cs can be held low permanently, low during the rd cycles, or it can be the same as rd . after initiating a conversion by bring- ing convst high, wait for eoc to go low (about 3.4? in internal clock mode) or 17 clock cycles (externalclock mode) before reading the first conversion result. read the conversion result by bringing rd low, which latches the data to the parallel digital output bus. bringrd high to release the digital bus. wait for the next falling edge of eoc (about 600ns in internal clock mode or three clock cycles in external clock mode)before reading the next result. when the last result is available, eolc goes low, along with eoc . wait three clock cycles, t quiet , before starting the next conver- sion cycle. reading after a conversion figure 6 shows the interface signals for a read operation after a conversion using an external clock. at the falling of eolc , on the 26th clock pulse after the initiation of a conversion, driving cs and rd low places the first con- version result onto the parallel i/o bus. read the conver-sion result on the rising edge of rd . successive low pulses of rd place the successive conversion results 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 16 ______________________________________________________________________________________ convst 17 18 19 20 21 22 23 24 25 26 27 29 t quiet ch3 ch2 ch1 ch0 t acc t req t convst sample clk t eoc1 t next t eoc eoc eolc rd d0?13 t rdl figure 5. reading during a conversion?nternal or external clock downloaded from: http:///
onto the bus. after reading all four channels, bring cs high to release the parallel i/o. after waiting t quiet , pulse convst low to initiate the next conversion. reference bypass the reference inputs as indicated in table 3. internal reference the internal reference supports all input ranges for themax1338. external reference implement external-reference operation by overdrivingthe internal reference voltage. override the internal ref- erence voltage by connecting a 2.0v to 3.0v external reference at ref. the ref input impedance is typically 5k ? . for more information about using an external ref- erence, see the transfer functions section. transfer functions digital correction factory trim procedures digitally shift the transfer func-tion to reduce bipolar zero-code offset to less than ? lsbs (typ). depending on initial conditions, the transfer function is shifted up or down, as required. the maximum shift that any transfer function experiences is 64 codes, which can have a small effect at the extremes of the transfer function, as shown in figure 7. max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 17 convst 1 29 26 31 ch3 ch2 ch1 ch0 t acc t convst sample clk t eoc eoc eolc d0?13 2 27 28 30 t clkh t clkl t cntc t clk only last pulse shown cs t quiet t rtc t rdh t rdl t ctr t eocrd t eolcrd rd t req figure 6. reading after a conversion?xternal clock location bypass capacitors refadc bypass capacitor to agnd 1nf refp1 bypass capacitor to agnd 0.1? refn1 bypass capacitor to agnd 0.1? refp1 to refn1 capacitor 1.0? com1 bypass capacitor to agnd 1.0? || 0.1? table 3. reference bypass capacitors downloaded from: http:///
max1338 input range settings table 4 shows the two? complement output for a selec- tion of inputs. the full-scale input range (fsr) depends on the select- ed range, and the voltage at ref, as shown in table 5. also shown in table 5 are the allowable common-mode ranges for the differential inputs. calculate the lsb size using: where a = gain multiplier for the selected input range, from table 6. determine the input voltage as a function of v ref , and the output code using:where a = gain multiplier for the selected input range, from table 6. figures 8, 9, 10, and 11 show the transfer functions for the four selectable input ranges. applications information layout, grounding, and bypassing for best performance, the board layout must followsome simple guidelines. separate the control i/o and parallel i/o signals from the analog signals, and run the clock signals separate from everything. do not run ana- log and digital (especially clock) lines parallel to one another, or digital lines underneath the adc package. run the parallel i/o signals together as a bundle. the max1338 has an exposed underside pad for a low-inductance ground connection and low thermal resistance. connect the exposed pad to the circuit board ground plane. figure 12 shows the recommend- ed system ground connections. establish an analog ground point at agnd and a digital ground point at dgnd. connect all analog grounds to the analog ground point. connect all digital grounds to the digital ground point. for lowest noise operation, make the power-supply ground returns as low impedance and as short as possible. connect the analog ground point to the digital ground point at one location. high-frequency noise in the power supplies degrades the adc? performance. bypass av dd to agnd with a parallel combination of 0.1? and 2.2? capacitors,bypass dv dd to dgnd with a parallel combination of 0.1? and 2.2? capacitors, and bypass drv dd to drgnd with a parallel combination of 0.1? and 2.2?capacitors. if the supply is very noisy use a ferrite bead as a lowpass filter, as shown in figure 12. vvv a code ain ain refadc __ + = 2 14 1 2 14 lsb av refadc = 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 18 ______________________________________________________________________________________ maximum64 codes +8191 0 -8192 0x2000 0x0000 0x1fff output code adjustedtransfer function initialtransfer function input voltage (lsbs) figure 7. example of digitally adjusted transfer functionshifted down to minimize zero-code offset 8 x v refadc 8 x v ref 2 14 1 lsb = two's complement binary output code -8192 -8190 +8191 +8189 0x2000 0x2001 0x2002 0x2003 0x1fff0x1ffe 0x1ffd0x1ffc 0x3fff 0x0000 0x0001 0 input voltage (v ain_+ - v ain_- in lsbs) -1 +1 figure 8. ?0v transfer function downloaded from: http:///
definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. for these devices, this straight line is a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulled. differential nonlinearity (dnl) differential nonlinearity is the difference between anactual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specifica- tion of less than ? lsb guarantees no missing codesand a monotonic transfer function. offset error offset error indicates how well the actual transfer func- tion matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero scale of the transfer function or at or near the midscale of the transfer function. for the max1338, the ideal zero-scale digital output transition from 0x3fff to 0x0000 occurs with an analog input voltage of zero. offset error is the amount of ana- log input-voltage deviation between the measured input voltage and the calculated input voltage at the zero- scale transition. max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 19 input voltage (v) ?0v input range selected ?v input range selected ?.5v input range selected ?.25v input range selected decimal equivalent output (code 10 ) two? complement binary output code 9.9988 4.9994 2.4998 1.2499 8191 01 1111 1111 1111 0x1fff 9.9976 4.9988 2.4997 1.2498 8190 01 1111 1111 1110 0x1ffe 0.0012 0.0006 0.0002 0.0001 1 00 0000 0000 0001 0x0001 0000 0 00 0000 0000 0000 0x0000 -0.0012 -0.0006 -0.0002 -0.0001 -1 11 1111 1111 1111 0x3fff -9.9988 -4.9994 -2.4998 -1.2499 -8191 10 0000 0000 0001 0x2001 -10.0000 -5.0000 -2.5000 -1.2500 -8192 10 0000 0000 0000 0x2000 table 4. code table with v ref = 2.500v selected input range (v) v refadc (v) full-scale input range (v) allowable common-mode range (v) 2.0 ? ? 2.5 ?0 ? ?0 3.0 ?2 ? 2.0 ? ?.5 2.5 ? ?.5 ? 3.0 ? ?.5 2.0 ? ?.25 2.5 ?.5 ?.25 ?.5 3.0 ? ?.25 2.0 ? ?.625 2.5 ?.25 ?.625 ?.25 3.0 ?.5 ?.625 table 5. input ranges selected input range (v) gain multiplier (a) lsb size (mv) ?0 8 1.2207 ? 4 0.6104 ?.5 2 0.1526 ?.25 1 0.0736 table 6. lsb size with v ref = 2.500v downloaded from: http:///
max1338 gain error gain error indicates how well the slope of the actualtransfer function matches the slope of the ideal transfer function. for the max1338, the gain error is the differ- ence between the measured positive full-scale and negative full-scale transition points minus the difference between the ideal positive full-scale and negative full- scale bipolar transition points. signal-to-noise ratio (snr) snr is a measure of the converter? noise characteris-tics. for a waveform perfectly reconstructed from digi- tal samples, snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (resid- ual error). the ideal, theoretical minimum analog-to-dig- ital noise is caused by quantization noise error only and results directly from the adc? resolution (n bits): 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 20 ______________________________________________________________________________________ 4 x v refadc 4 x v ref 2 14 1 lsb = two's complement binary output code -8192 -8190 +8191 +8189 0x2000 0x2001 0x2002 0x2003 0x1fff0x1ffe 0x1ffd0x1ffc 0x3fff 0x0000 0x0001 0 input voltage (v ain_+ - v ain_- in lsbs) -1 +1 figure 9. ?v transfer function 2 x v refadc 2 x v ref 2 14 1 lsb = two's complement binary output code -8192 -8190 +8191 +8189 0x2000 0x2001 0x2002 0x2003 0x1fff0x1ffe 0x1ffd0x1ffc 0x3fff 0x0000 0x0001 0 input voltage (v ain_+ - v ain_- in lsbs) -1 +1 figure 10. ?.5v transfer function v refadc v ref 2 14 1 lsb = two's complement binary output code -8192 -8190 +8191 +8189 0x2000 0x2001 0x2002 0x2003 0x1fff0x1ffe 0x1ffd0x1ffc 0x3fff 0x0000 0x0001 0 input voltage (v ain_+ - v ain_- in lsbs) -1 +1 figure 11. ?.25v transfer function digital power supplies av dd agnd dgnd +5v digital circuits ferritebead +5v dv dd gnd max1338 +5v +3v gnd agnd analog power supply drv dd drgnd figure 12. power-supply grounding and bypassing downloaded from: http:///
snr = (6.02 x n + 1.76)db where n = 14 bits. in reality, there are other noisesources such as thermal noise, reference noise, and clock jitter. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist frequency exclud- ing the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad indicates the converter? noise and distortionperformance. sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the global accuracy of an adc at a spe- cific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full- scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is a dynamic indication of how much harmonicdistortion the converter adds to the signal. thd is the ratio of the rms sum of the first five harmon- ics of the fundamental signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 ? 6 are the amplitudes of the 2nd- through 6th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the funda- mental (maximum signal component) to the rms value of the next largest spurious component, excluding dc offset. sfdr is specified in decibels relative to the car- rier (dbc). aperture delay aperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. channel-to-channel isolation channel-to-channel isolation indicates how well eachanalog input is isolated from the others. the channel-to- channel isolation for the max1338 is measured by applying a dc -0.5dbfs sine wave to the on channel while a high frequency 10khz -0.5dbfs sine wave is applied to all off channels. an fft is taken for the on channel. from the fft data, channel-to-channel crosstalk is expressed in db as the power ratio of the dc signal applied to the on channel and the high-fre- quency crosstalk signal from the off channels. power-supply rejection (psrr) psrr is defined as the shift in gain error when the ana- log power supply is changed from 4.75v to 5.25v. small-signal bandwidth a -20dbfs sine wave is applied to the max1338 input.the frequency is increased until the amplitude of the digitized conversion result decreases 3db. full-power bandwidth a -0.5dbfs sine wave is applied to the max1338 input.the frequency is increased until the amplitude of the digitized conversion result decreases 3db. thd vvvvv v log = ++++ ?? ?? ? ? ?? ?? ? ? 20 2 2 3 2 4 2 5 2 6 2 1 enob sinad . . = 176 602 sinad db signal noise distortion rms rms () log ( ) = + ?? ?? ?? ?? 20 max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 21 downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc 22 ______________________________________________________________________________________ max1338 ain3- ain0+ain0- ain1+ ain1- ain2+ ain2- ain3+ d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 av dd agnd dv dd dgnd av dd av dd refadc refp1 com1 +5v gnd +5v gnd d13 wr rd analog inputs p arallel i/o cs eolc control i/o 13 12 11 10 5 4 3 2 6, 8, 14, 16, 18, 20, 28 27 23 21 5351 50 5449 48 47 46 45 52 4241 40 39 38 37 36 35 34 33 32 31 30 29 55, 56 15 av dd av dd 7 1 0.1 f 0.1 f 0.1 f 1.0 f 0.001 f 0.1 f intclk/extclk shdn clk convst eoc standby digital i/o digital output +3v to +5v gnd 0.1 f 44 43 drgnd drv dd 26 24 25 1.0 f 0.1 f 22 0.1 f 0.1 f 0.1 f 0.1 f 9 17 19 refp2 refn2 refn1 com2 t ypical operating circuit downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc ______________________________________________________________________________________ 23 4948 47 46 45 44 43 2223 24 25 26 27 28 36 37 38 39 40 41 42 7 6 5 4 3 2 1 max1338 thin qfn top view ain0+ av dd ain0- ain1+ ain1- agnd av dd cs wr rd eolc eoc drgnd drv dd d13d12 d11 d10 d9 d8 d7 agnd refn2 refn1 com2 com1 refp2 refp1 1516 17 18 19 20 21 14 13 12 11 10 9 8 29 30 31 32 33 34 35 5655 54 53 52 51 50 refadc agnd av dd agnd av dd agnd intclk/extclk av dd agnd ain2+ ain2- ain3+ ain3- agnd dgnd dgnd dv dd shdn standby clk convst d6d5 d4 d3 d2 d1 d0 pin configuration chip information transistor count: 27,000process: bicmos exposed pad: connect to agnd downloaded from: http:///
max1338 14-bit, 4-channel, software-programmable, multiranging, simultaneous-sampling adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 56l thin qfn.eps downloaded from: http:///

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